Atomic transistors based on seamless lateral metal-semiconductor junctions with a sub-1-nm transfer length

Abstract

The edge-to-edge connected metal-semiconductor junction (MSJ) for two-dimensional (2D) transistors has the potential to reduce the contact length while improving the performance of the devices. However, typical 2D materials are thermally and chemically unstable, which impedes the reproducible achievement of high-quality edge contacts. Here we present a scalable synthetic strategy to fabricate low-resistance edge contacts to atomic transistors using a thermally stable 2D metal, PtTe₂. The use of PtTe₂ as an epitaxial template enables the lateral growth of monolayer MoS₂ to achieve a PtTe₂-MoS₂ MSJ with the thinnest possible, seamless atomic interface. The synthesized lateral heterojunction enables the reduced dimensions of Schottky barriers and enhanced carrier injection compared to counterparts composed of a vertical 3D metal contact. Furthermore, facile position-selected growth of PtTe₂-MoS₂ MSJ arrays using conventional lithography can facilitate the design of device layouts with high processability, while providing low contact resistivity and ultrashort transfer length on wafer scales.

Introduction

The scaling of the dimensions of electronic components is essential to increase the density of devices in an integrated chip (IC)^1,2. To fulfill industrial requirements, the transistors in ICs must have both ultrashort physical lengths of the gate (L < ~12 nm) and contact (L_c, which should be smaller than the required tightest metal pitch, ∼16 nm) by 2034^1,3. In this respect, two-dimensional (2D) van der Waals (vdW) materials have emerged because of their higher carrier mobility and superior electrostatic controllability at the atomically thin limit^1,2 to achieve channel scaling for future nanoelectronics. However, fundamental limitations in producing ultra-scaled, low-resistance contact electrodes for 2D semiconductors (e.g., transition metal dichalcogenides (TMDs))^2,4 using a conventional 3D metal contact limit the switching performance of transistor. For example, the deposition of the 3D metal contact onto 2D semiconducting TMDs typically yields a disorder-rich interface at the metal-semiconductor junction (MSJ), resulting in high contact resistance (R_c)^2,4. Furthermore, the resultant 3D/2D MSJs have inevitably long transfer length (L_T) of charge carriers (e.g., L_T > ∼50–200 nm)^5,6,7,8,9,10, which leads to an exponential increase in R_c with the reduction in the contact size if L_c is smaller than L_T (i.e., L_c < L_T), prohibiting prospective contact scaling.

To avoid the problems associated with conventional vertical contact, pioneering works on the use of edge-to-edge connected lateral 3D-2D (or 2D-2D) MSJs have been conducted^{5,11,12,13,14,15,16,17}. It has a directly metalized junction with strong hybridization, and the absence of atomic discontinuities or defects at the lateral MSJs facilitates superior contact between the 2D semiconducting TMDs and metal electrodes (i.e., smaller R_c)^5,11,13. Furthermore, using a lateral MSJ has a significant advantage in lowering the L_T because the carriers are only injected through the few-atom-thick interface (i.e., L_T decreases to a few nm). Thus, the lateral MSJ-based transistor performs excellently even if L_c is reduced to the sub-nm range⁵. However, owing to the general thermal and chemical instability of TMDs, practical techniques for controlling heterogeneous integration are highly challenging. Only proof-of-concept has been demonstrated^{5,11,13,14,15,16,17}, thereby failing to achieve high yield and high device density. For instance, obtaining edge contact by lithographic techniques requires that the 2D semiconductors be protected against oxidizing conditions using a passivation layer (e.g., hexagonal boron nitride)^11,13, or in-situ etching prior to edge metallization⁵.

Chemical vapor deposition (CVD) of TMD-based 2D-2D MSJ heterostructures lacks the control of spatial locations^12,14,15, and their active layer is inevitably degraded by thermal budget effect because the synthesis of 2D semiconductors along the edge of 2D vdW metals are still at the embryonic stage of development. Although graphene has been widely studied for low-resistance contacts with 2D semiconductors^16,17, the large lattice mismatch between graphene and the 2D semiconductor, along with the polymer-based residues incorporated into the assemblies during the graphene-transfer processes, commonly hinder the production of edge-contacted in-plane 2D-2D MSJs and limit the performance of the contacts^16,18. Recent studies have demonstrated significant advances towards fabricating lateral 2D-2D MSJs using irregularly-formed flakes of 2D vdW metals, Mo₂C and VS₂^14,15. However, for the approach to be practical and scalable, limitations in terms of the reproducibility of conformal MSJ patterns with sub-1-nm L_T on a large scale and low R_c through the suggested approach need to be addressed. Therefore, in the long term, it is vital to develop a groundbreaking technique for fabricating a 2D vdW metal with high stability and processability that can offer a substantial degree of freedom in the device architecture.

Here, we demonstrate the formation of synthetic edge contacts consisting of metallic 2D vdW PtTe₂ crystals with high thermal stability and the facile position-selected growth of conformal lateral 2D-2D MSJ patterns using conventional lithography. We investigated the high thermal stability of PtTe₂ under ultrahigh vacuum (UHV) (which maintained its intrinsic surface property up to ∼825 °C) and succeeded in obtaining edge-directed PtTe₂-MoS₂ lateral heterojunctions by using two-step CVD. The resultant epitaxially grown lateral MSJ sustained almost ideal stoichiometry without the development of thermally induced voids or the production of mixed alloys. The monolayer MoS₂ MSJ transistors with PtTe₂ edge contacts exhibited superior n-type carrier transport compared to those with 3D vertical contacts, attributed to both the reduced thermionic emission at the Schottky barrier and the lack of interfacial defects. Additionally, the position-controlled growth of PtTe₂ and subsequent chemical assembly to MoS₂ allowed us to obtain 2D TMD-based synthetic edge contact arrays on a large scale. The patterned MSJ showed ultralow contact resistivity (> 11.7 Ω·μm²), which is almost one order of magnitude smaller than those of typical 3D top contact electrodes (∼10³ to 10⁵ Ω·μm²), along with a significantly short L_T (∼0.7 nm), indicating the potential of PtTe₂ for affording drastically miniaturized high-quality metal contacts to atomic transistors.

Results

Synthetic strategy for high-quality, edge-contact MSJ

To produce electronic-grade edge contacts, we developed a synthesis method for lateral MSJs that ensures high-quality MoS₂ as a channel material. Many previous studies on lateral MSJs prepared using CVD rely on the growth of 2D metals after the preparation of 2D semiconductors because typical 2D semiconductors (e.g., WS₂, MoSe₂) require a relatively high growth temperature (∼700–800 °C) compared to vdW metals (e.g., ∼600 °C for NbS₂ or VSe₂)^19,20. However, this sequence for two-step CVD can thermal degrade 2D semiconductors, substantially lowering the performance of resultant device because of the increased chalcogen vacancies of the channel²¹. Instead, we developed a technique to create a 2D semiconductor (i.e., MoS₂) after preparing 2D metal (i.e., PtTe₂) to produce a high-quality semiconducting 2D sheet in the lateral MSJ (Fig. 1a, b).

Fig. 1: Formation of MoS₂–PtTe₂ lateral heterostructure by two-step growth.

a Schematic of the growth process for the PtTe₂ flakes at a growth temperature of 700 °C. b Schematic of the growth process of MoS₂ along the edge of PtTe₂. The insets of (a) and (b) show the representative false-colored scanning electron microscopy (SEM) image of the synthesized PtTe₂ flakes and PtTe₂-MoS₂ heterostructures on SiO₂/Si substrate. c Raman spectra of multilayer PtTe₂ flakes displaying strong E_g and A_1g signals (vertical dashed lines) without any substantial differences up to 900 °C annealing under UHV conditions. d Benchmark plots of metallic TMDs such as 1T’-WTe₂^31,35, 2H-NbSe₂^32,37, 1T’-MoTe₂^33,38, 1T-TaS₂^36,39, and 1T’-MoS₂³⁴ with respect to the room-temperature electrical resistivity (ρ) and the endurance temperature, T, that the material can tolerate without structural degradation. The endurance T of the metallic TMDs were characterized under vacuum (solid) or Ar atmosphere (binned). e Confocal Raman spectrum captured at the heterojunction’s interface, PtTe₂, and MoS₂ flakes. The vertical lines indicate E_g and A_1g modes from PtTe₂, and E_2g and A_1g modes from MoS₂. f Atomic force microscopy (AFM) height profile along the red line displayed in the corresponding AFM image (inset, with a scale bar of 2.5 μm; the MoS₂ boundary is indicated as white dashed lines.), indicating the synthesized MoS₂ forms a monolayer (H ≈ 0.78 nm) while the PtTe₂ forms multiple layers (thickness, H ≈ 28 nm). g, h X-ray photoelectron spectroscopy (XPS) analysis of the PtTe₂-MoS₂ heterostructure. For comparison, the spectra of bare MoS₂ grown independently on the substrate and those of Ti-deposited MoS₂ are displayed. The XPS profiles of the for Mo 3d, and S 2p regions are shown in (g) and (h), respectively. The XPS Mo 3d_3/2, Mo 3d_5/2, S 2p_1/2, and S 2p_2/3 peaks are specified by dashed lines. i, j Transmission electron microscopy (TEM) investigations of the heterostructure consisting of a multilayer PtTe₂ with a monolayer MoS₂. i Selected area electron diffraction (SAED) patterns of the MoS₂-PtTe₂ heterostructure, showing the orientationally aligned (100) and (110) planes of each material, indicating the epitaxial growth of the MoS₂. j (left) High-angle annular dark-field scanning-TEM (HAADF-STEM) image demonstrating the atomic arrangements at the MoS₂-PtTe₂ heterojunction. (right) Schematic of the lateral heteroepitaxy aligned to the <100> direction.

As an efficient edge contact metal for MoS₂, we selected one of 2D metallic TMDs, PtTe₂, because it exhibits many attractive features as potential n-type metal contacts for 2D semiconductors. For example, the theoretical work function (WF) of few-layered PtTe₂ (WF; ∼4.56–4.57 eV)²² is one of the smallest among those reported for chemically synthesizable metallic TMDs^23,24,25 (Supplementary Fig. 1), and its electrical conductivity (>10⁶ S/m) has shown to be the highest among 2D metals^26,27. However, the simultaneous achievement of large-area production of high-quality stoichiometric, metallic TMD thin films with thermal stability remains challenging, mainly because of the difficulties in incorporating Te and low environmental stability during thermal CVD^28,29. Furthermore, guaranteeing the thermal stability of the 2D metal is essential for our two-step CVD process because PtTe₂ must resist the thermal procedure required for synthesizing of MoS₂ while maintaining excellent quality. In this regard, no success has been achieved yet for 2D-2D lateral heterojunctions based on 2D tellurides.

Since Te vacancies substantially reduce the Gibbs free energy for the adsorption of ambient gas and cause structural instability³⁰, the growth of high-quality PtTe₂ is essential to ensure its stability to some extent. Thus, we synthesized the PtTe₂ crystals using the eutectic solidification method^26,31, where the pre-deposited Pt precursor reacted with liquefied Te at 700 °C (Fig. 1a). The resultant PtTe₂ formed single crystals with a highly stoichiometric nature (Supplementary Fig. 2). As our synthetic methods do not require an oxide precursor, no oxygen-metal bonds, which often become reactive sites and cause poor stability, were formed³². In addition, the PtTe₂ crystals maintained their high-quality structures with Te terminations even after exposure to air for up to ∼3 h, as indicated by TEM analysis (Supplementary Fig. 3). The WF of PtTe₂ (∼4.65 eV), characterized by ultraviolet photoelectron spectroscopy (UPS), was comparable to the computed value²² (Supplementary Fig. 2h), satisfying the basic requirement of an efficient n-type contact for the MoS₂ transistor, considering its band structure (Supplementary Fig. 1).

To evaluate the thermal stability of the as-synthesized PtTe₂, the crystal was annealed under UHV conditions (∼10⁻¹⁰ Torr) at temperatures between T = 500–1000 °C for 1 h. The Raman spectra obtained are shown in Fig. 1c. The as-grown PtTe₂ and the UHV-annealed crystals heated to 900 °C showed comparable Raman in-plane E_g (∼110 cm⁻¹) and out-of-plane A_1g (∼156 cm⁻¹) vibrational modes of PtTe₂²⁷ (black dashed line in Fig. 1c). Remarkably, only annealing above ∼1000 °C altered the peak positions and their intensities, demonstrating the high thermal stability of the PtTe₂. The thermal stability is an intrinsic property independent of the thickness and degree of structure order, as evaluated by X-ray photoelectron spectrum (XPS) and UPS (Supplementary Fig. 4). The surface properties of PtTe₂ start to change above the T of ∼825 °C, which is far beyond the limitations of metallic TMDs (e.g., WTe₂, MoTe₂, TaS₂, and 1 T’-MoS₂) measured under vacuum or in an Ar atmosphere^{32,33,34,35,36}. In addition, low electrical resistivity of PtTe₂ (ρ ≈ 0.37 mΩ·cm; Supplementary Fig. 5a, b), even lower than other few-layered metallic TMDs^{31,34,37,38,39} (ρ ≈ 0.5–100 mΩ·cm), shows promise for a robust electrode that may prevent thermal stress as summarized in Fig. 1d.

Following the synthesis of thermal-stable PtTe₂ multilayers, a monolayer of MoS₂ was formed laterally along the edge of the PtTe₂ by CVD at ∼700 °C (Fig. 1b). Compared to the edge, the atomically pristine, dangling-bond-free surface of a 2D crystal typically possesses fewer surface defects and minimal MoS₂ nucleation. Density functional theory (DFT) simulations were performed to investigate the selective nucleation of MoS₂ on the edges of PtTe₂. Adsorption energy calculations reveal that there was preferential adsorption and subsequent nucleation of MoS₂ at the PtTe₂ edge. For instance, the MoS₂ monomer exhibited a lower adsorption energy of −3.6 eV at the PtTe₂ edge compared to −2.7 eV on the PtTe₂ basal plane (Supplementary Fig. 6). These findings are consistent with those of previous reports on the two-step CVD of 2D heterostructures, where in the adsorption energy of 2D TMDs at the edge of a 2D crystal was lower than that on the 2D basal plane^19,40. The low occurrence of MoS₂ nucleation on the PtTe₂ surface is attributed to the higher adsorption energy of MoS₂ nuclei on the basal plane. In our experiments, we significantly lowered the mass flux of precursors through the source-contact geometry and use of a MoO_x thin-film precursor significantly reduced the opportunities for nucleation (Supplementary Note 1). The attachment of adatoms or atomic clusters of MoS₂ by heterogeneous nucleation was allowed only at the edge of PtTe₂. The introduction of a higher mass flux would thus increase the possibility of producing more nucleations⁴¹ and trigger the synthesis of randomly distributed multilayer MoS₂ on the structures.

Attributed to the edge-mediated growth mode, the MoS₂ crystals were observed exclusively along the PtTe₂ edges as shown in false-colored scanning electron microscopy (SEM) images (inset of Fig. 1b and Supplementary Fig. 7). The Raman signals at the interface of MSJ demonstrated the strong signals of PtTe₂ without variation in positions, while the MoS₂ features of E_2g (∼384 cm⁻¹) and A_1g (∼407 cm⁻¹) modes also existed (Fig. 1e). Most of the MoS₂ attached to PtTe₂ was a monolayer with a uniform thickness of ∼0.7 nm, as shown in the AFM image and height profile (Fig. 1f). XPS analysis of the heterostructures was used to reveal the surface compositions and chemistries (Fig. 1g, h and Supplementary Fig. 8). The XPS spectra of the MoS₂ layer did not show a substantial peak shift compared to that of non-stitched bare flakes (green, Fig. 1g, h). In comparison, the vertically deposited 3D metals on MoS₂ can induce surface defects^4,42, that is, a non-stoichiometric layer (i.e., Mo_xS_y) or alloys (i.e., Ti_xS_y), as we experimentally demonstrated in the case of Ti/MoS₂ (gray, Fig. 1g). Hence, the coincident binding energy of MoS₂ connected to PtTe₂ and that of the bare flakes suggests that the present growth mode conferred the intrinsic surface properties of the 2D semiconductor layer (i.e., MoS₂), as the MoS₂ layer was grown after preparing PtTe₂.

XPS analysis further revealed no noticeable change in the stoichiometry of PtTe₂ after thermal CVD for MoS₂ (at. % (Te/Pt) ≈ 1.80). This high stability of PtTe₂ during thermal CVD was also confirmed by SEM-EDS characterization (Supplementary Fig. 7d). Pt and Te were the only two observed elements, and there were no apparent variations in their stoichiometry (that is, averaged at. % (Te/Pt) = 1.90 ± 0.06). In addition, we electrically characterized PtTe₂ to verify that the influence of the high-temperature process was negligible (Supplementary Fig. 5c, d). The sustained low ρ (≈ 0.35 mΩ·cm) and the weak dependence on gate voltage (V_g) imply that exposure to chemical species (MoO_x and S) does not degrade PtTe₂ (Supplementary Fig. 5d). Back-scattered SEM analysis did not show any traces of in-plane mixed alloying (Supplementary Fig. 7e–h), further demonstrating the high stability of PtTe₂.

Structural analysis conducted using transmission electron microscopy (TEM) also confirmed the high quality of the PtTe₂-MoS₂ lateral heterostructure (Fig. 1i, j, and Supplementary Figs. 9–11). We found that the MoS₂ monolayer grew epitaxially along the edge of PtTe₂ single crystal using the selected area electron diffraction (SAED) pattern (Fig. 1i), indicated by the two aligned sets of hexagonal diffraction spots with six-fold symmetry reflecting the epitaxially aligned (110) and (100) lattice planes. Atomic-resolution analysis was performed using high-angle annular dark-field scanning-TEM (HAADF-STEM) (Fig. 1j). The 2H-MoS₂ was atomically stitched to 1T-PtTe₂ without void-like defects. The high stoichiometry and compositional consistency of PtTe₂ were also confirmed by the STEM-EDS mapping and spectra (Supplementary Fig. 9a–f). The electron energy loss spectroscopy (EELS) line scan further revealed the abrupt compositional change at the junction (Supplementary Fig. 9g–i). Cross-sectional TEM analysis of synthetic MSJ also provided identical insight into the edge-to-edge connected structure, demonstrating in-plane epitaxial growth of MoS₂ and sharp interface at the junction (Supplementary Fig. 10). Remarkably, the absence of mixed or alloyed structures in the as-synthesized MSJ implies that our synthesis approach was successful. This also demonstrates the merit of our approach compared to those adopted in previous studies^14,16,18 (as summarized in Supplementary Table 1). Interestingly, the high density of dangling bonds at the PtTe₂ edge generated several MoS₂ basal planes that were attached vertically to the edges of the PtTe₂ flakes (Supplementary Fig. 11). However, the vertical MoS₂ layers were relatively insignificant in the synthesized results because most MSJs possessed laterally stitched components without vertical structures.

We performed DFT calculations to understand the formation mechanism of defect-free interface in the lateral PtTe₂-MoS₂ MSJ (Supplementary Fig. 12). The calculated relative energies (ΔE) of the possible intermediates (i.e., MoO_x and S adsorbents) attached to the PtTe₂ edge indicated the relative stability of each atomic structure during the epitaxial growth of MoS₂ (Supplementary Table 2). We found that reactive gas-phase S atoms were bound to MoO₃ precursor attached to the edge of PtTe₂ (ΔE < −2.88 eV), and that O in MoO₃ tended to desorb as it reacted with additional S by forming SO₂(g) because of the consequent exothermic processes. A similar repeated reduction process for MoO_3-x resulted in the formation of the most stable MoS₂ structure because of the substantial energy relative to the initial structure (ΔE = −19.49 eV). Furthermore, each periodic interfacial cell comprised four PtTe₂ and five MoS₂ unit cells to minimize the lattice mismatch at the heterojunction (Supplementary Fig. 13). The lattice mismatch between PtTe₂ and MoS₂ was ∼18% when each unit cell of PtTe₂ was matched to a unit cell of MoS₂ in a one-to-one ratio according to the equation λ = (|a₁ − a₂ | )/a₂, where a₁ (∼3.25 ± 0.05 Å) and a₂ (∼3.96 ± 0.05 Å) are the in-plane lattice constants of MoS₂⁴³ and PtTe₂⁴⁴, respectively (Supplementary Fig. 13a). In comparison, adjusting the number of unit cells on the interface to a five-to-four ratio of MoS₂ and PtTe₂ resulted in a smaller mismatch between the materials (∼3%). STEM analysis also validated our heterostructure with consistently matched periodic cells along the <100> direction, indicating a (semi-)coherent interface (Supplementary Fig. 13b–d). Given this smaller interfacial cell mismatch (∼3%), we calculated the most stable atomic structure for the heterostructure using DFT and the multicell model, as depicted in Supplementary Fig. 13b, c. The Pt-S and Mo-Te covalent bonds formed at the interface, resulted in strong orbital interactions between the atoms at the heterojunction.

High-performance monolayer MoS₂ FETs with PtTe₂ edge contact

We now shift our focus to the electrical characterization of the edge-contacted 2D-2D MSJ field-effect transistors (FETs). After the definition of MoS₂ channels by the reactive ion etching process, PtTe₂-flake-connected MoS₂ MSJ FETs were fabricated by Ti/Au (10/70 nm) contact pad deposition on PtTe₂. The Ti/Au layer was also deposited on the other side of the MoS₂ channel to produce an asymmetrical contacted MoS₂ channel with a fixed width (W) and length (L) for comparison with the MoS₂-Ti vertical junction (Fig. 2a, b). The gate bias was applied through the 300-nm-thick SiO₂ dielectric layer for this measurement. Because the reverse-biased contact (source) causes most of the voltage drop and dominates the transistor behavior in n-type MoS₂ MSJ FETs, the source (either Ti or PtTe₂) determines the performance of a FET with asymmetric contacts. This allows the electrical properties of the barrier to be systemically evaluated by controlling the interface^15,29. We selected Ti as the counterpart to PtTe₂ because it is the most widely used contact and has a low WF of ∼4.33 eV²³, which is even smaller than that of PtTe₂ (∼4.60-4.65 eV in Fig. 1g).

Fig. 2: High performance of edge-contacted PtTe₂-MoS₂ metal-semiconductor junction (MSJ) field-effect transistors (FETs).

a–h Monolayer MoS₂ FETs with asymmetric carrier injection from PtTe₂ lateral epitaxial contact and from vertical Ti, characterized at room temperature. a Schematic and (b) optical microscopy image of a device with asymmetric Ti/Au and PtTe₂ electrodes contacted to a monolayer MoS₂ (white dashed lines) with a defined channel width (W) and length (L). c, e Cross-sectional illustrations of resistance networks of monolayer MoS₂-based MSJ with (c) atomically stitched PtTe₂ lateral contact and (e) top-contact with Ti/Au. Metallization of MoS₂ can degrade both the contact resistivity (ρ_c) and sheet resistance (R_sh) of MoS₂. In contrast, the PtTe₂-MoS₂ heterostructure has simpler resistance components, and the chemically derived edge resistance (R_edge) is the only series resistance for the channel (R_ch). d, f Comparison of band alignments with different Schottky barrier heights (SBHs) and Schottky barrier width (SBW) with respect to the MoS₂ conduction band (CB) and valance band (VB) edges for (d) PtTe₂-MoS₂ heterostructure and (f) conventional 3D metal-contacted MoS₂. Tunneling barrier formed by vdW gap between Ti and MoS₂ (T_vdW) and defect-induced deep levels are displayed in (f). g Drain current (I_ds) as a function of gate voltage (V_g) for PtTe₂-MoS₂ (red) and Ti/MoS₂ (blue) MSJ FETs on the logarithmic (lines; left) and linear (symbols; right) scales. h Summary of the field-effect mobility (μ_FE) and on-state current (I_on) of FETs with different carrier injections from PtTe₂ (red) and Ti (blue). The error bars indicate the standard deviations from each device set. i, j SBH of PtTe₂-MoS₂ MSJ extracted using thermionic emission model. i Calculated thermionic barrier height of PtTe₂-MoS₂ (red) and Ti/MoS₂ MSJ (blue) as a function of V_g showing the low SBH of 38.5 meV at the flat band voltage. Inset: representative Arrhenius plot (ln(I_ds/T^3/2) vs. 1/k_BT) of PtTe₂-MoS₂ heterojunction with different V_g. j Comparison of the SBH of few-layer MoS₂ based MSJ FETs with 3D top contacts (Ti^47,48,49, Cr⁴⁸, Ag⁴⁹, Au⁴⁸, and Pd⁴⁸; solid) and with 2D lateral contacts (Mo₂C¹⁵, and graphene^16,17; open). The extracted SBHs of PtTe₂-MoS₂ (red) and Ti/MoS₂ (blue) are indicated by colored symbols. Plots of the strength of Fermi-level pinning (S = |d(SBH)/d(WF)|) are shown as solid lines in order to compare the mechanism of formation of the SBHs.

Figure 2g shows a representative transfer characterization (I_ds-V_g) of the MSJs where the electrons were injected from the PtTe₂ edge (red) and the vertical Ti contact (blue). In addition to the output curve (Supplementary Fig. 14a), the on-state current (I_on) of PtTe₂-MoS₂ (∼4.0 μA/μm) was twice that of Ti-MoS₂ (∼1.8 μA/μm). The two-terminal field-effect mobility (μ_FE) was also increased to ∼9.7 cm² V⁻¹ s⁻¹ by injection of charge carriers from PtTe₂, compared to Ti (∼7.0 cm² V⁻¹ s⁻¹) for the same channel (∼3.5 ± 1.3 cm² V⁻¹ s⁻¹ and ∼1.6 ± 0.9 cm² V⁻¹ s⁻¹ on average for more than 10 devices with PtTe₂ and Ti asymmetric contacts, respectively; and the averaged values are demonstrated in Fig. 2h). We found a slight negative shift of the turn-on voltage when the PtTe₂ source electrode was selected. This negative shift reflects the improved carrier injection from the contact^45,46 because the reduced R_c and SBH caused the transistor easier to switch on (note that we could not observe an obvious doping effect on the in the XPS (Fig. 1g, h) and Raman spectra (Fig. 1e) after lateral epitaxy of PtTe₂). The performance enhancement was also confirmed for the MoS₂ FET with symmetric contact geometry (i.e., PtTe₂-MoS₂-PtTe₂; Supplementary Figs. 14b–e). It showed a μ_FE of ∼15.8 cm² V⁻¹ s⁻¹, higher than those from asymmetrically contacted FET, which again verifies the influence of the resistance of the FET components related to Ti.

High-energy deposition of a 3D metal typically degrades the surface of monolayer MoS₂ by forming sulfur vacancies and promoting atomic diffusion at MSJs^4,42 (i.e., forming interfacial defects of Ti/MoS₂ as shown in Fig. 1g, h). These processes increase the R_sh and contact resistivity (ρ_c) by forming localized states as depicted in the contact components in Fig. 2e, f^29,47,48,49. In addition, the established gap states can shift the charge neutrality, pinning the Fermi level to the mid-gap of MoS₂, which can significantly impact the Schottky barrier height (SBH)^48,50. According to Sze’s model⁵¹, the Fermi level pinning (FLP) strength increases with the density of interfacial traps (D_it; Supplementary Fig. 15 and Supplementary Note 2); thus, the large D_it in our Ti/MoS₂ MSJ FETs could induce strong FLP to the mid-gap states, and therefore resulted in a large SBH and lower thermionic emission efficiency over the SB. Furthermore, the top contact scheme has a long path for carrier transfer (e.g., wide width of the barriers, BW), leading to a larger R_sh and ρ_c. The vdW gap between the 3D metal and 2D semiconductor can also produce an additional tunnelling barrier (T_vdW), although Ti/MoS₂ may possess a narrower T_vdW than other 3D metals/MoS₂ because of the strong hybridization^2,42. In contrast, the PtTe₂-MoS₂ MSJ developed herein has a cleaner interface that prevents further metallization on the MoS₂ surface (i.e., absence of R_sh), leading to simple contact components only related to the edge (Fig. 2c, d)^5,11. The absence of T_vdW and the reduced BW can improve carrier injection through the edge of PtTe₂. Notably, despite the presence of a vdW gap between PtTe₂ and the metal contact pad (i.e., Ti/Au in Fig. 2a), the contribution of R_c in the Ti/PtTe₂ interface (∼0.12–0.23 kΩ·μm) of the MoS₂-based MSJ system was insignificant (∼0.13%; Supplementary Fig. 16). Furthermore, the estimated R_c of the Ti/PtTe₂ interface is almost the lowest value that can be obtained in a 3D metal/vdW metal interfacial system (Supplementary Table 3) and is even smaller than that obtained with the most widely used vdW metal (graphene).

To gain insight into the physical characteristic associated with carrier transport through the barriers, the thermionic barrier heights (ϕ_B) of the monolayer MoS₂ MSJ FETs with symmetric contacts of PtTe₂ and Ti were calculated by electrical characterization at low temperatures (Fig. 2i, j and Supplementary Fig. 17). This allowed us to extract the SBHs at the interface by fitting the Arrhenius plot to the thermionic emission model⁴⁸:

$${I}_{{ds}}=\left[A{A}^{*}{T}^{3/2}{{\exp }}\left(-\frac{q{\phi }_{B}}{{k}_{B}T}\right)\right]\left[{{\exp }}\left(\frac{q{V}_{{ds}}}{{k}_{B}T}\right)-1\right]$$

(1)

Here, A is the junction area, and A^* is the effective Richardson–Boltzmann constant. According to Eq. (1), the ϕ_B can be extracted from the slope of the Arrhenius plot (inset of Fig. 2i), resulting in ϕ_B as a function of V_g (Fig. 2i). Interestingly, the ϕ_B for PtTe₂-contacted MSJ at the flat band voltage (V_FB) was found to be a substantially small value of ∼35.9 ± 9.8 meV (average of four devices), where the primary carrier injection mechanism changed from the thermionic transport (V_g < V_FB) to tunneling (V_g > V_FB, where the linear V_g-ϕ_B relation ends at this actual SBH). For V_g values exceeding ∼30 V, ϕ_B was negative, indicating tunneling-dominant electrical transport through the reduced SBW of the edge contact, which is difficult to achieve with the 3D metal contact owing to the wider BW and the presence of T_vdW for the latter. For example, the SBW at the PtTe₂-MoS₂ interface (∼0.94 nm) calculated using a classical model for Schottky diodes was smaller than that of the Ti/MoS₂ MSJ FETs (∼1.5 nm) (Supplementary Note 2).

The extracted SBH (ϕ_Bat V_FB) of ∼35.9 meV is considerably lower than that of the Ti/MoS₂ MSJ (∼125 meV) and almost one order of magnitude smaller than previously reported values for other 3D-metal/MoS₂ MSJ^47,48,49 (≈100–500 meV in Fig. 2j). Deep energy level states were established primarily because the interface was degraded by penetration of the 3D metals into the MoS₂ band^29,47,48,49 (Fig. 2f). Therefore, the SBH of the FETs with Ti contact was much higher than the ideal value calculated by applying the Schottky-Mott rule (e.g., SBH = WF – χ ≈ 0 meV, where χ is the electron affinity of monolayer MoS₂ (≈ 4.28 eV)⁴⁸). The deviation from the Schottky-Mott rule is substantial for 3D contacts; thus, SBHs cannot be effectively modulated by selecting the 3D metals, as the Fermi levels are pinned to the shifted charge-neutral level (CNL). The interface index, S (=|d(SBH)/d(WF)|), indicates the extent of the deviation⁴⁸, which approaches zero for the 3D metal contacts (blue line in Fig. 2j). This strong FLP (S ≈ 0) agrees well with the theoretical model prediction⁵¹ that the S value decreases with increasing interfacial defect density (D_it ≈ ∞). We found that the increase in D_it due to the replacement of the edge PtTe₂ by a top Ti contact could approach ∼1.13 × 10¹³ eV⁻¹ cm⁻², and gave rise to a stronger FLP (Supplementary Fig. 15 and Supplementary Note 2).

Compared with vertical 3D metal contacts, the synthetic edge contact can weaken the FLP because of the lowered dimensionality with fewer interfacial defects^10,13,50,52 Hence, the SBHs can follow the ideal Schottky-Mott limit to some extent (S = 1; red line in Fig. 2j), enabling the formation of tiny SBHs by using low-WF 2D metals. Furthermore, the impact of strong covalent bonds at the edge interface, which may result in a slight deviation from the perfect Schottky-Mott limit through the formation of a metal-induced gap state (MIGS)¹³, is less significant compared to that at the top contacts because of the 1D-like atomically thin interface (Supplementary Fig. 18). Accordingly, the SBH in all 2D lateral contacts (Mo₂C¹⁵, and graphene^16,17) to few-layer MoS₂ MSJ FETs produced by CVD (∼26-45 meV) is much smaller than those of vertical 3D contacts (Fig. 2j). Similarly, the FLP-free PtTe₂ edge interface allowed the achievement of a negligible SBH (∼35.9 meV) due to low WF of PtTe₂ (∼4.56 eV²²); this is one of the lowest WF values among 2D metals, as summarized in Supplementary Fig. 1. This smaller SBH (∼35.9 meV) enabled improved thermionic emission and tunneling transport through the SB compared with the top-contact Ti/MoS₂, which had a higher SBH (∼135 meV) and additional T_vdW. A higher μ_FE and on/off ratio was therefore achieved, as indicated by variation of carrier transport through the barriers with V_g (Supplementary Fig. 19).

Spatial arrangement of synthetic edge contacts

As the ultimate approach for demonstrating the advantage of PtTe₂ with respect to material processing, we eventually controlled the spatial arrangement of the synthetic edge contacts at the microscopic level (Fig. 3a). Powder-based tellurization was used to transform the Pt patterns prepared by conventional photolithography into PtTe₂ patterns at a low temperature of ∼400 °C (here, we used Pt instead of PtO_x, which can assure high quality of the resultant PtTe₂³²). Remarkably, the patterns were successfully manufactured on a 2-inch SiO₂/Si wafer, which is vital for achieving scalable, mass production of PtTe₂ electrodes in any desired shapes (Fig. 3b). The electrical characterization by the four-point probe method showed that the R_sh of the as-synthesized PtTe₂ thin film was H-dependent due to the greater carrier scattering as H decreased (Fig. 3c). The R_sh values of the developed PtTe₂ samples were lower than those previously reported for CVD-grown films⁵³, and comparable to those of single-crystalline flakes²⁷, suggesting that the developed films are of high quality. We found that the XPS-extracted stoichiometries for 4-nm-thick PtTe₂ were almost perfect (at.% ratio of Te/Pt ≈ 2) independent on the thermal stress up to T ≈ 825 °C (Fig. 3d), suggesting the high quality and thermal stability of the film (similar to the case for single crystals in Fig. 1). The R_sh of the PtTe₂ thin film was also ∼450 Ω/sq for the samples annealed below 800 °C. However, it suddenly changed as T reached 850 °C (R_sh ≈ 208 Ω/sq), indicating the atomic displacements of Te (which begins to resemble the electrical properties of Pt, as noted in caption of Supplementary Fig. 4).

Fig. 3: Wafer-scale growth of PtTe₂ patterns for synthetic edge contact arrays.

a Schematic of procedure for realizing PtTe₂-MoS₂ heterostructure arrays in a position-controllable manner, involving photolithography before the tellurization of Pt. b Photograph image of as-grown large-scale PtTe₂ patterns on a 2-inch-scale SiO₂/Si substrate (left), and representative OM images of the thin film captured on the left image (right). c Sheet resistance (R_sh) of as-grown PtTe₂ thin film as a function of the film thickness (H), characterized by four-probe method. R_sh values for high-quality PtTe₂ from previous reports^27,53 are displayed for comparison. The inset shows a representative AFM image of the as-grown thin film (scale bar: 1 μm). d (left) XPS-derived atomic ratio of the thin film, showing the nearly ideal stoichiometry of PtTe₂ (at. % (Te/Pt) ≈ 2; dashed red line) irrespective to T up to 825 °C, (right) R_sh of thin films as a function of annealing T, with R_sh ~467 Ω/sq (for T = 500 °C) indicated with a blue dashed line. e Representative OM images of MoS₂ monolayer laterally contacted to the edge of polycrystalline PtTe₂ thin film patterns with H ≈ 4 nm, in the form of fully stitched thin film depending on the growth conditions. f Representative Raman spectrum of PtTe₂-MoS₂ heterostructure, showing strong signals of each material, e.g., E_g (110.2 cm⁻¹) and A_1g (156.5 cm⁻¹) peaks of PtTe₂ and E_2g (384.5 cm⁻¹) and A_1g (402.3 cm⁻¹) modes of MoS₂. g, h TEM analysis of heterostructure with patterned PtTe₂ (H ≈ 4 nm) and monolayer MoS₂. g HAADF-STEM image of heterostructure showing epitaxially stitched PtTe₂ and MoS₂ without void-like defects along both surfaces. h Diffractogram corresponding to interface region, indicating orientationally aligned (100) and (110) planes in each atomic structure.

Subsequent conducted thermal CVD of MoS₂ induces lateral epitaxy of monolayer MoS₂ from the edge of the arranged PtTe₂ patterns (Fig. 3e). A key to achieving a fully stitched MoS₂ thin film between the PtTe₂ crystals (instead of small flakes) is the extension of the growth time while decreasing the deposition rate via delicate control of the atomic flux. A higher growth temperature (>730 °C) and extensive precursors (for MoO_x and S) resulted in multilayer MoS₂ and alloyed MoS₂/PtTe₂ structures due to the island growth mode, whereas the layer-by-layer growth mode was enabled by the opposite manner. Figure 3f shows a representative Raman spectrum of the heterojunction, which shows the vibrational modes of each layered crystal. The Raman peaks for MoS₂ in the flakes and at the interface did not differ significantly (e.g., the energy difference between E_2g and A_1g peaks ≈ 19 cm⁻¹), suggesting the growth of monolayer MoS₂. The HAADF-STEM image (Fig. 3g) and its indexed diffractogram (Fig. 3h) confirm epitaxial alignment between monolayer MoS₂ and PtTe₂. The STEM(-EDS) and corresponding (inverse) FFT study also verified the formation of a well-stitched lateral heterojunction comprising high-quality atomic layers (Supplementary Fig. 20). We did not find any significant differences from the bare MoS₂ flake in the XPS characterization of MoS₂ grown along the PtTe₂ array (Supplementary Figs. 8c, d).

Transport in the edge-contacted PtTe₂-MoS₂ MSJ FET arrays

Arrays of FETs composed of edge-contacted MSJs patterns were fabricated and operated by using an Al₂O₃ back-gate dielectric (Fig. 4a). Analysis of the output and transfer characteristics (Fig. 4b, c) showed that the monolayer MoS₂ FETs with PtTe₂ symmetric contacts exhibited a maximum μ_FE value of ∼17.9 cm² V⁻¹ s⁻¹ (∼10.6 ± 2.9 cm² V⁻¹ s⁻¹ on average), I_on of up to ∼3.4 μA/μm (∼2.3 ± 0.3 μA/μm) and I_on/I_off in the range of ∼10⁷ to 10⁸, which are much higher than those fabricated using vertical Ti contacts on monolayer MoS₂ FETs with the same device geometries (channel L and W). We repeatedly observed performance enhancement for a large number of devices (>15), where the averaged μ_FE of the Ti/MoS₂ FET was ∼0.4 ± 0.3 cm² V⁻¹ s⁻¹ and the I_on was ∼0.2 ± 0.1 μA/μm (Fig. 4d). It is worthwhile to note that, considering their L and L_T values, the μ_FE value of the MoS₂ FETs with PtTe₂ edge contacts were either comparable or even higher than those of previously reported devices with various 3D edges (e.g., Sc⁵⁴, Ti⁵⁰, Au¹⁰, and Mn¹³) or 2D lateral contacts (e.g., graphene (Gr.)^17,18,55,56, and VS₂¹⁴) (Supplementary Figs. 21a–c).

Fig. 4: Electrical transport studies of the edge-contacted PtTe₂-MoS₂ MSJ FETs array.

a Schematic showing monolayer MoS₂ FETs with patterned PtTe₂ edge contacts (upper) and vertical Ti contacts (lower). The transfer length (L_T) of the carrier and physically attained contact length (L_c) are schematically demonstrated. b Representative I_ds–V_ds characteristics of monolayer MoS₂ FET with symmetric PtTe₂ and Ti contact electrodes depending on V_g. c I_ds–V_g characteristics of corresponding devices on linear (symbols; right) and logarithmic scale (lines; left). d Average μ_FE and I_on of different FETs (>15 devices) contacted to PtTe₂ (red) or Ti (blue). The error bars indicate the standard deviations of each measurement set. e–g Determination of contact resistance (R_c) of MSJs with different compositions using (e, f) TLM and (g) Y-function method. e TLM plot showing total resistance normalized by contact width (RW) as a function of L. The y-intercept yields the 2R_c in units of Ω ∙ μm. Inset shows OM image of MoS₂ (purple-like) grown between edges of PtTe₂ patterned for TLM. (f) TLM-derived R_c of PtTe₂-MoS₂ MSJ FETs approaching ~168 ± 127 kΩ∙μm when the carrier density (n_2D) of ~9 × 10¹² cm⁻² was largely induced by V_g (red circles), which is significantly lower than that of Ti/MoS₂ (~4,285 ± 1,959 kΩ∙μm, blue squares). Solid lines specify curves fitted to the relation of R_c depending on the n_2D (R_c ∝ n_2D^−0.5)². g Histograms of R_c for PtTe₂-MoS₂ (left) and Ti/MoS₂ MSJ FETs (right) extracted by the Y-function method (Supplementary Fig. 22). The lowest R_c of PtTe₂-MoS₂ obtained in this study was ~18.2 kΩ·μm and the average value reached ~113.0 ± 60.3 kΩ·μm. h Benchmark specific contact resistivity (ρ_c) and L_T of synthetic PtTe₂ contacts. The experimental data from MoS₂ FETs with lateral graphene contact (Gr.^16,55), 3D edge contacts (Ti¹¹, Ni⁵, Au¹⁰, Sc⁵⁴, and Mn¹³), and top contacts (Ti^6,58, Ni⁵⁹, Au^7,10, Ag⁹, and Mn¹³) are demonstrated. The colored symbols are the extracted data for PtTe₂ (red stars) and Ti (blue circle) in this work. For fair comparison, the data are sorted by ρ_c extraction methods, i.e., four-point probe (open), TLM (solid), and Y-function (half-open symbol).

To determine whether the μ_FE of a device was severely underestimated because of the contact property, we extracted the intrinsic mobility (μ₀) of more than 30 different devices using the Y-function method (Supplementary Fig. 22). The μ₀ value is typically free from underestimation due to R_c and provides a better indication of the intrinsic performance^11,55,57. The averaged μ₀ value in our PtTe₂-MoS₂ MSJ FETs was calculated to be ∼11.1 ± 4.5 cm² V⁻² s⁻¹, which is almost comparable to the μ_FE values (∼10.6 ± 2.9 cm² V⁻² s⁻¹) calculated using the transconductance (g_m = ∂I_ds/ ∂V_g). The insignificant difference between μ_FE and μ₀ (∼4.5%) implies the presence of a minor contact barrier at the edge interface.

Notably, by using a MSJ fabricated with transfer length method (TLM) patterns, we could determine the R_c values of the monolayer MoS₂ FETs with PtTe₂ edge contact (Fig. 4e, f). The TLM-driven R_c reached ∼168 ± 127 kΩ·μm when a carrier density (n_2D) of ∼9 × 10¹² cm⁻² was attained, which was largely induced by a V_g of ∼19 V. This R_c value is ∼25 times lower than that of its counterpart using Ti (∼4,285 ± 1,959 kΩ·μm) in Fig. 4f. We note that the demonstration of R_c as a function of n_2D (= C_ox(V_g-V_th)/q) helps compare devices because n_2D includes information on the threshold voltage (V_th) that can be varied by channel doping, the gate dielectric layer, and the interfacial trap density of the substrate^2,6,7. The R_c was also calculated using the Y-function method^11,55,57 (Fig. 4g and Supplementary Fig. 22), where the minimum R_c of the device was ∼18 kΩ·μm (∼113 ± 60 kΩ·μm, on average) and ∼2,562 kΩ·μm (∼12,443 ± 8,406 kΩ·μm) for PtTe₂-MoS₂ and Ti/MoS₂, respectively. The average R_c values were comparable to those extracted from the TLM, demonstrating the reliability of the characterization methods. The low R_c obtained with PtTe₂ allowed the FETs to outperform the Ti/MoS₂ MSJ FETs (Fig. 4b–d).

The significantly low TLM-driven R_c at the monolayer-thick interface (e.g., L_T ≈ 0.7 nm) of the spatially-arranged PtTe₂-MoS₂ MSJ suggests that the contact length (L_c) can be further scaled without an increase in R_c (Fig. 4h), as an advantage. For 3D top contacts, R_c increases as the L_c decreases below the L_T because current crowding becomes severe, according to the transmission line model^6,7 expressed as R_c = $\sqrt{{\rho }_{c}{R}_{{sh}}}$cot(L_c/L_T), where L_T = $\sqrt{{\rho }_{c}/{\rho }_{{sh}}}$ and ρ_c (= R_c ∙ L_T) is the specific contact resistivity (Supplementary Fig. 23). Thus, there have been tremendous efforts (i.e., insertion of an interlayer⁶, chemical doping^58,59, and metal deposition under UHV conditions⁷) to achieve immunity of R_c to L_c scaling by lowering both ρ_c and L_T (right panel in Fig. 4h). However, the achievement of a small L_T (< tens of nanometers) together with low ρ_c is inherently challenging for 3D top contacts^8,9,10. Instead, the edge contact can prospectively afford a negligible L_T because carrier transport occurs strictly through the interface of the edge^5,11,13 as depicted in Fig. 4a.

We summarize the device performances of MoS₂ FETs with 3D edge^{5,10,11,13,50,54} or 2D lateral contacts^{14,15,16,17,18,55,56} (Supplementary Table 5). Although a direct comparison of the contact properties with our device is inappropriate because of the differences in the L_T values, MoS₂ channel thicknesses, and R_c-extraction methods (see Supplementary Note 3 for more details), the developed PtTe₂-MoS₂ MSJ had a significantly low ρ_c (as low as ∼11.7 Ω·μm²) and L_T ≈ 0.7 nm, which is the lowest value among those reported for few-layer MoS₂ FETs with 2D lateral graphene^16,55, or 3D edge (Ti¹¹, Ni⁵, Au¹⁰, Sc⁵⁴, and Mn¹³) contacts (see the left panel in Fig. 4h and Supplementary Fig. 21d), thus promising the realization of ultralow R_c in L_c-scaled transistors for next-generation 2D nanoelectronics. We propose that even further reduction of R_c and SBH is possible in our PtTe₂ edge contact by achieving a multilayer lateral 2D-2D MSJ heterostructure, which can be attributed to the effectively screened interfacial traps from the substrates^13,60, the downshift of the conduction band edge in multilayer MoS₂²⁹, and the weaker current crowding at the thicker heterointerface^{6,7,8,9,10,13}. Moreover, the use of high-k dielectrics (e.g., HfO₂, Sb₂O₃, SrTiO₃), passivation layers (e.g., BN), and top-gate structures, which were already applied in the previous edge-contact FETs^{10,11,13,18,55}, can also improve the performance of our device, which can be due to the suppressed charge scattering and trapped states from surrounding disorders⁶⁰.

Discussion

We report here a spatially-controlled, reproducible preparation of metallic vdW PtTe₂ crystals as a lateral edge contact with semiconducting monolayer MoS₂. The high-quality stoichiometric PtTe₂ retained its surface properties even after CVD at the high temperature of ∼750 °C under UHV conditions. The edge of thermally stable PtTe₂ provides nucleation sites for the subsequently grown 2D semiconductor without noticeable thermal degradation, resulting in in-plane lateral MSJs without substantial interfacial issues such as alloying or void-like defects. Therefore, the PtTe₂-MoS₂ MSJ may have a simple resistance network and displays superior n-type carrier transport through the short and narrow thermionic barriers, enabling the higher performance of the FET compared to that composed of vertical 3D contacts. This approach also provides a more scalable way to produce an arrangement of lateral heterostructures in a dimension-controlled manner, where the contact properties could be evaluated by using the TLM patterns consisting of the lateral MSJ. The substantially small contact resistivities achieved through the atomically thin edge suggest that the developed contact scheme has the potential for scaling the contact length for miniaturized 2D electronics.

Our work on the synthesized edge-contact MSJ arrays offers benefits in terms of scalability for both material synthesis and device fabrication. The edge contact between 2D (or 3D) metals and 2D semiconductors should be developed and evaluated based on CVD-grown 2D layers to investigate its practical potential for semiconductor technology in the future. However, almost all investigations on lateral MoS₂-based MSJs have drawbacks in terms of reproducibility or the achievement of pure edge contact (Supplementary Table 4). In this regard, our strategy based on direct growth of a large-area 2D metal on a dielectric substrate followed by MoS₂ epitaxy has considerable advantages over other methods using 2D metals such as Mo₂C¹⁵ and graphene^{16,17,18,55,56}, formed by mechanical exfoliation of single crystal and/or transfer of CVD-grown layers. More importantly, the realization of pure edge contacts with the L_T reduced to ∼1 nm using graphene^{16,17,18,55,56} or VS₂¹⁴ is highly challenging because of the inevitable laterally overlapped junction or alloyed structures.

In addition, the construction of TLM patterns using a TMD-based synthetic edge contact provides assurance by permitting a better systematic analysis. Because of the complexity of realizing a lateral MSJ, it is difficult to achieve reproducible data from multiple devices and to perform statistical computations for R_c^{10,11,13,14,15,16,18,54,55}. Investigating R_c of edge-contact MSJs using TLM pattern proves particularly challenging because of channel-to-channel variations and deficiencies in integration scalability. Many of the studies on lateral MSJ rely on the four-point measurement^{10,13,14,15,16,18,54} or Y-function methods^11,55 for R_c extraction, which can be inaccurate compared with the TLM (Supplementary Note 3). Therefore, together with the reproducibility of our 2D material system, the statistical analysis of the R_c values extracted by TLM and the Y-function method in this study can provide better insights into the electrical features of 2D-2D edge contacts.

Methods

Growth of PtTe₂ flakes

The growth of multilayer PtTe₂ single crystals was conducted using a conventional horizontal furnace system, in which the Te-Pt precursors on a SiO₂/Si substrate were placed inside the center of the chamber. To prepare the precursor sample, a Pt thin film precursor (∼2 nm, 99.9% purity pellet) was deposited using an e-beam evaporator (Temescal FC-2000), and then 0.1 g of Te powder was introduced manually to cover up the thin film. The reactant was then heated to ∼700 °C (at a heating rate of ∼50 °C/min) under a pressure of ∼0.1 Torr using H₂ (10 sccm) as the carrier gas. After maintaining a growth temperature of ∼700 °C for 1 min, the furnace was naturally cooled to room temperature. We succeeded in synthesizing PtTe₂ directly on top of the SiO₂/Si substrate because the unreacted Te was vaporized and sucked out toward the vacuum pump.

Preparation of patterned PtTe₂ thin films

The pre-deposited, poly-crystalline Pt thin film (∼1 nm) on the SiO₂/Si substrate and Te powder (∼0.1 g) inside a quartz boat were placed in a horizontal furnace ∼1 cm apart. Under low pressure (0.1 Torr) at ∼400 °C, the evaporated Te vapor reacts with the Pt precursor, resulting in a homogenous, uniform PtTe₂ layer with a thickness of ∼4 nm. The thickness of the as-grown thin film could be controlled by modulating the Pt precursor’s thickness. For position-controllability, the shape of any desired pattern was defined using photolithography (MIDAS MDA-400S) with a photoresist with an undercut profile (DPRi-1549), followed by Pt deposition and lift-off. Using the same method for thin films, the shaped Pt precursor could be tellurized, resulting in successful growth of the PtTe₂ patterns.

Synthesis of MoS₂ along the edge of PtTe₂

The MoS₂ flakes were synthesized using MoO₃ thin film (∼1 nm-thick on a 1 cm² SiO₂/Si substrate, evaporated using an e-beam evaporator) and S powder as precursors in atmospheric-pressure two-zone CVD with Ar/H₂ as the carrier gas. To promote the nucleation of MoS₂, ∼1 μL of a 0.01 M NaCl promoter solution was pipetted on the corner of the oxide thin film on the substrate. Then, the NaCl solution was baked at ∼100 °C to evaporate the water entirely. The formerly prepared PtTe₂ multilayers on the substrate were placed face to face on top of the MoO₃ film prepared with NaCl. This metal oxide/PtTe₂ sample was placed at the center of the heat zone of the furnace, with the S-powder-containing boat loaded upstream of the CVD furnace. Under an Ar/H₂ ratio of 70/20 sccm, the system was steadily heated to ∼700 °C. At a growth temperature of ∼700 °C, S vapor was introduced because the powder was heated at ∼200 °C just before reaching the growth temperature and then maintained constantly for a growth time of ∼10 min. The as-synthesized PtTe₂ sample was stored in a chamber under UHV atmosphere (∼10¹⁰ Torr) immediately after synthesis, and the air exposure time of PtTe₂ until the subsequent CVD process was <5 min.

Structural characterization

The morphological investigation was conducted using an SEM (Hitachi S-4800 or Su8220) equipped with high- and low-angle BSE detectors. Micro-Raman measurements were performed with a 532 nm laser (Thermo Scientific DXR2 Raman Microscope) configured for wavenumber precision of ≤0.066 cm⁻¹. XRD patterns were captured using a Bruker AXS D8 instrument with a Cu Kα source. AFM images were recorded on a Bruker Dimension AFM operating in tapping mode. High-resolution STEM images, SAED patterns, EDS were obtained using an aberration-corrected FEI Titan³ G2 60-300 equipped at an acceleration voltage of 200 kV. Noises of high-resolution STEM images were subtracted by Wiener filter. EELS was performed using a Gatan Quantum 965 dual EELS system with an energy resolution of 1.0 eV under an acceleration voltage of 200 kV. Specimen for cross-section TEM analysis were prepared by focused ion beam (FEI Helios Nanolab 450HP). XPS and UPS measurements were performed using an ESCALAB 250XI system (ThermoFisher K-alpha) equipped with an Al X-ray source under UHV conditions. The calibration of the XPS was performed by the alignment of the C 1 s spectrum (whose binding energy is 284.5 eV).

DFT calculation

We constructed a 4 × 4 × 1 PtTe₂ supercell with vacuum along the b and c directions to model a PtTe₂ single layer strap with an edge having 50% Te coverage. We performed geometry optimization based on DFT calculations using the supercell and the Vienna ab initio software packet⁶¹ (VASP) code. We employed the projector-augmented-wave (PAW) method⁶² and the Perdew-Burke-Enzerhof (PBE) functional⁶³ using a plane-wave basis set with an energy cutoff of 500 eV. The k-points were sampled using a 4 × 4 × 1 Monkhorst-Pack mesh⁶⁴, and the spin-orbit coupling effect was also included.

Electrical device fabrication and measurements

To define the device channel, the shape of the channel layer was defined by e-beam lithography (NBL and NB3), and then a reactive ion etching process was conducted using SF₆ and O₂ plasma. The etched structures were transferred to a dielectric layer on highly p-doped Si, which can be used as the back-gate. For instance, the single-crystalline PtTe₂-MoS₂ MSJ was transferred to a 300-nm-thick SiO₂ layer, whereas the conformally grown array was transferred to a 50-nm-thick Al₂O₃ layer. The well-connected heterointerface between PtTe₂ and MoS₂ confirmed through TEM analysis (Figs. 1j and 3g), proves that the wet transfer method utilizing a polymeric supporting layer did not affect the edge contact of the samples. The SiO₂ layer was dry-oxidized in a furnace (KHD-306) with ±3% uniformity, and the Al₂O₃ dielectric layer was prepared by atomic layer deposition (Lucida, D100), being deposited within ±2% uniformity along the wafer. Ti/Au (∼10 and ∼70 nm, respectively) contacts and pads were then deposited using e-beam lithography and an e-beam evaporator. Electrical characterizations at different temperatures (138-300 K) were performed using a Keithley 4200-SCS detector in a cryogenic probe station (Lakeshore CRX-4K) under a high vacuum (∼10⁻⁶). The μ_FE of the FETs on the Al₂O₃ dielectric insulator were determined by measuring the gate oxide capacitance per unit area (C_ox) of Al₂O₃ via C-V analysis of the metal-insulator-semiconductor structure (e.g., Pt/Al₂O₃/p⁺⁺Si), where the DC voltage was swept from −5 to 10 V, while an AC voltage with an amplitude of ∼100 mV and frequency of ∼20 kHz was applied. The calculated C_ox in the accumulation region was 0.164 ± 0.001 μF cm⁻² (average of ten devices), which corresponds to an equivalent oxide thickness of ∼117.9 nm.